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? semiconductor MSC7170-01 1/27 fedl7170-03 ? semiconductor MSC7170-01 5 7 dot character 16-digit 2-line display controller/driver with keyscan function general description the MSC7170-01 is a display controller/segment driver containing a 5 6 keyscan circuit, designed for a 5 7 dot matrix type vacuum fluorescent (vf) display tube. use of the msc1164 grid driver allows a maximum of 16-digit pair to be displayed, or use of the msc7171 grid driver allows a maximum of 12 digit pairs to be displayed. features ? able to display 5 7 dot matrix type characters of a maximum of 16 digits 2 lines (when msc1164 is used) ? the number of display digits selectable in a range of 1 digit 2 lines to 16 digits 2 lines ? standby function combination of the msc7171 grid driver and the MSC7170-01 decreases grid driver current during the standby mode of the driver. ? display intensity selectable by 10-bit digital dimming ? display characters selectable from among 256 types by internal pla ? 8-bit synchronous serial data transfer spi interface ?5 6 keyscan circuit ? driver output current (i oh ) : 1 ma (seg1 to seg35) : C15 ma (seg36) ? supply voltage : v dd = 5 v 10% : v disp = 60 v (max.) ? package: 100-pin plastic qfp (qfp100-p-1420-0.65-bk) (product name: MSC7170-01gs-bk) fedl7170-03 this version: sep. 2000 previous version: nov. 1997
? semiconductor MSC7170-01 2/27 fedl7170-03 block diagram kbint 5 6keyboard scanner v dd reset enable simo sclk somi 12345 123456 row col 8 8 shift register 8 latch command decoder controller timing generator osc v ss2 osci osco sync row 1 cursor data buffer 16b row 2 display data buffer 16w 8b 8 latch latch 8 8 row 1 display data buffer 16w 8b row 2 cursor data buffer 16b character generator 256w 35b 5 8 8 4 5 address selector 5 write address counter read address counter 4 8 444 digit count register address compare duty cycle counter duty and blank generator blank latch 35 seg driver latch 36 seg driver grid driver interface ac filament sync v disp seg1-1 seg1-2 seg1-36 seg2-1 seg2-2 seg2-36 v ss1 data clock duty 35 36 standby
? semiconductor MSC7170-01 3/27 fedl7170-03 pin configuration (top view) note: segn-x sequence depends on rom code content and may be altered by changing segment number x relationship to rom bit number. see correspondence between segment output and vf display tube dots. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 v disp seg 2-21 seg 2-22 seg 2-23 seg 2-24 seg 2-25 seg 2-26 seg 2-27 seg 2-28 seg 2-29 seg 2-30 seg 2-31 seg 2-32 seg 2-33 seg 2-34 seg 2-35 seg 2-20 seg 2-19 seg 2-18 seg 2-17 seg 2-16 seg 2-15 seg 2-14 seg 2-13 seg 2-12 seg 2-11 seg 2-10 seg 2-9 seg 2-8 seg 2-7 seg 2-6 seg 2-5 seg 2-4 seg 2-3 seg 2-2 seg 2-1 seg 2-36 seg 1-1 seg 1-2 v ss1 seg 1-3 seg 1-4 seg 1-5 seg 1-6 seg 1-7 seg 1-8 seg 1-9 seg 1-10 seg 1-11 seg 1-12 sync data clock duty standby v ss2 seg 1-21 seg 1-36 seg 1-22 seg 1-23 seg 1-24 seg 1-25 seg 1-26 seg 1-27 seg 1-28 seg 1-29 seg 1-30 seg 1-31 seg 1-32 seg 1-33 seg 1-34 seg 1-35 seg 1-20 seg 1-19 seg 1-18 seg 1-17 seg 1-16 seg 1-15 seg 1-14 seg 1-13 v dd row1 row2 row3 row4 row5 col1 col2 col3 col4 col5 col6 kbint enable simo sclk somi reset osci osco 100-pin plastic qfp
? semiconductor MSC7170-01 4/27 fedl7170-03 pin descriptions pin symbol description 1v disp high voltage power supply 2-36 seg2-1 to seg2-35 vf tube 5 7 dot anode driver outputs. these pins may be connected directly to the vf tube. 37 seg2-36 vf tube cursor driver output. 38-39 seg1-1 seg1-2 vf tube 5 7 dot anode driver outputs. these pins may be connected directly to the vf tube. 40 v ss1 high voltage ground 41-72 seg1-3 to seg1-35 vf tube 5 7 dot anode driver outputs. these pins may be connected directly to the vf tube. 73 seg1-36 vf tube cursor driver output. 74 seg1-21 vf tube 5 7 dot anode driver output. this pin may be connected directly to the vf tube. 75 v ss2 logic supply ground. 76 standby grid driver standby output pin. a logic high level on this output forces the grid driver (msc7171) into a low power standby mode. 77 duty duty cycle output pin. 78 clock grid driver clock output pin. 80 sync ac filament synchronization input pin. 81 osco oscillator output pin. 82 osci oscillator input pin. 83 reset reset input pin. 84 somi spi data output pin. keyscan data is shifted out on the falling edge of sclk. 85 sclk spi clock input pin. data is shifted in on the simo pin on the rising edge of sclk. 86 simo spi data input pin. command data is shifted in on the rising edge of sclk. chip select input pin. interface to the microprocessor is possible only when a logic low level is applied to this pin. the somi output pin is tri-stated when enable is at a logic high level so that multiple devices may use the spi network. 87 enable interrupt request output to the microprocessor for keyscan data read out. keyscanning is started when any key is depressed or released. after completion of one cycle, kbint goes to a logic low level to indicate new keyscan data is available. kbint remains low until execution of keyscan data output command. 88 kbint column 1-6 input pins from key switch matrix. a pull-up resistor is built in so that the pin is in the logic high state except when a key is depressed and a logic low level is input to the pin. 89-94 col6-1 79 data grid driver data output pin. connects to crystal (or ceramic resonator) oscillator and capacitor. these pins have internal feedback resistors.
? semiconductor MSC7170-01 5/27 fedl7170-03 pin symbol description row 1-5 scanning signal output pins to key switch matrix. when any key is depressed or released, keyscanning is started and is continued until keyscan data output command is executed. all row 1-5 outputs go to logic low level when keyscanning is stopped. 95-99 row5-1 100 v dd logic voltage supply.
? semiconductor MSC7170-01 6/27 fedl7170-03 absolute maximum ratings parameter symbol condition rating unit logic supply voltage v dd C0.3 to 6.0 v driver supply voltage v disp C0.3 to 65 v input voltage v in applies to all inputs C0.3 to v dd +0.3 v power dissipation p d ta 25 c 663 mw seg1-1 to seg1-35 C2 ma driver output current seg2-1 to seg2-35 C2 ma seg1-36, seg2-36 C15 ma storage temperature t stg C65 to 150 c package thermal resistance r j-a 98 c/w *1 *1, 2 *1 *3 notes: *1 voltage that can be applied to gnd *2 stresses beyond the rating may cause permanent damage to the device. *3 package thermal resistance between junction and atomsphere. junction temperature t j in the following expression must not exceed 150 c: t j = p r j-a + ta (p: maximum ic power consumption) recommended operating conditions parameter symbol condition range unit logic circuit supply voltage v dd usable only for logic power terminal 4.5 to 5.5 v driver supply voltage v disp usable only for driver power terminal 7 to 60 v operating temperature t op C40 to 85 c
? semiconductor MSC7170-01 7/27 fedl7170-03 electrical characteristics dc characteristics unit max. min. condition symbol parameter v 0.7 v dd v ih "h" input voltage v 0.3 v dd v il "l" input voltage "h" input current m a 1 C1 v dd =5.5 v v in =v dd i ih1 m a 30 C30 i ih2 "l" input current m a 1 C1 v dd =5.5 v v in =0.5 v i il1 m a C160 C15 i il2 "h" output voltage v v dd C0.6 i oh =C500 m a v oh1 v v disp C3 i oh =C1 ma v oh2 v v disp C4 i oh =C15 ma v oh3 v 4 i oh =C200 m a v oh4 "l" output voltage v v ss +0.6 i ol =500 m a v ol1 v 2.5 i ol =100 m a v ol2 v 3 i ol =3 ma v ol3 v 0.5 i ol =200 m a v ol4 power supply ma 10 all segs on, 16-digit display, maximum brightness, no load, f osc =4 mhz i dd1 ma 10 all segs off i dd2 m a 25 low power mode i dd3 ma 15 i disp1 m a 1 all segs off i disp2 (ta=C40 to 85 c, v dd =4.5 to 5.5 v, v disp =7 to 60 v) all inputs all inputs simo, sclk, enable , reset col1 6, sync simo, sclk, enable , reset col1-6, sync osco segn-1 to n-35, n=1, 2 seg1-36, seg2-36 duty, somi, kbint data, clock, standby osco segn-1 to n-35, n=1, 2 seg1-36, seg2-36 row1-5, duty, somi, kbint ,data, clock, standby applied pin v dd Cv ss v disp Cv ss all segs on, 16-digit display, maximum brightness, no load, f osc =4 mhz
? semiconductor MSC7170-01 8/27 fedl7170-03 ac characteristics (1/2) (ta=C40 to 85c, v dd =4.5 to 5.5v, v disp =7 to 60 v, f osc =4 mhz, 12-digit display) unit enable setup time max. typ. min. condition symbol parameter t es see fig. 1 (data transfer timing) 50 ns enable hold time t eh see fig. 1 (data transfer timing) 4 m s sclk frequency t cp see fig. 1 (data transfer timing) 0.5 2 mhz sclk pulse width t cw see fig. 1 (data transfer timing) 250 ns sclk rise/fall time t cr /t cf see fig. 1 (data transfer timing) 500 ns simo setup time t ds see fig. 1 (data transfer timing) 50 ns simo hold time t dh see fig. 1 (data transfer timing) 120 ns somi output enable t oe enable to somi valid 200 ns somi output disable t od enable to somi tri-state 200 ns sclk to somi delay t pd see fig. 1 (data transfer timing) 100 ns byte length t byte msb to lsb see fig. 2 (example of data transfer) 3.5 m s byte delay t delay msb to lsb see fig. 2 (example of data transfer) 20 m s sync frequency t sync duty cycle=50%, f osc C4 mhz 12-digit display 0.4 250 khz segn pulse width t seg f osc =4 mhz see fig. 5 (duty cycle timing) c i =20pf 10 m s operating frequency t osc self-oscillation 1.5 4 4.5 mhz duty period t grid f osc =4 mhz, see fig. 3 (12-digit display cycle timing) 256 m s blank interval (min.) t blank f osc =4 mhz see fig. 3 (12-digit display cycle timing) t blank =48/f osc 12 m s data pulse width high t dw f osc =4 mhz see fig. 5 (duty cycle timing) 256 m s data period t data f osc =4 mhz see fig. 3 (12-digit display cycle timing) 3072 m s data to clock delay t dc f osc =4 mhz see fig. 5 (duty cycle timing) 5 m s clock pulse width t pw f osc =4 mhz see fig. 5 (duty cycle timing) 250 m s clock cycle t clock f osc =4 mhz see fig. 5 (duty cycle timing) 256 m s keyscan cycle time t scan f osc =4 mhz see fig. 6 (keyscan timing) 40 m s *1
? semiconductor MSC7170-01 9/27 fedl7170-03 ac characteristics (2/2) (ta=C40 to 85c, v dd =4.5 to 5.5 v, v disp =7 to 60 v, f osc =4 mhz, 12-digit display) unit keyscan pulse width max. typ. min. condition symbol parameter t spw f osc =4 mhz, see fig. 6 (keyscan timing) 8 m s ceramic resonator crystal keypress to kbint at "l" level f osc =4 mhz 5 10 ms wake-up time t wake 0.5 1.3 5 m s 1 3.4 5 m s t r t f c l =20 pf, v disp =60 v, v ol =6 v, v oh =50 v slew rate (segn-1 to segn-35) 0.2 5 m s 0.1 5 m s t r t f c l =20 pf, v disp =60 v, v ol =6 v, v oh =50 v slew rate (segn-36) v ol =0.1 v dd , v oh =0.9 v dd , c l =10 pf 5 20 200 ns t r /t f slew rate (duty, data, clock) all pins 6pf c i input capacitance *1) for the minimum value when digits other than 12 digits are displayed, refer to the following expression. t sync (min) > f osc 1024 (digit display number)
? semiconductor MSC7170-01 10/27 fedl7170-03 timing diagram enable 3.8v 0.8v simo 3.8v 0.8v sclk 3.8v 0.8v somi 3.8v 0.8v t es t ds t dh t cw t cw t cr t eh t cp t oe t od t cf t pd figure 1. data transfer timing enable somi sclk simo s6 s5 s4 s3 s2 s1 s0 c7 c6 c5 c4 c3 c2 c1 c0 s7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 c7 t byte t delay figure 2. data transfer example duty data clock t data t grid t blank figure 3. 12-digit (n=12) display cycle timing
? semiconductor MSC7170-01 11/27 fedl7170-03 duty data t grid t blank clock grid1 figure 4. grid1 interval timing data clock t dgl t pw t dgh duty gridn (f osc ) segn-1 to n-35 segn-36 grid12 t dc t blank t seg grid1 note: (f osc ) is internal to the msc7170 and not visible externally. gridn are outputs of, and t dgl and t dgh are timig parameters of, the msc7171 (grid driver). figure 5. duty cycle timing
? semiconductor MSC7170-01 12/27 fedl7170-03 row1 row2 t scan row3 row4 row5 kbint t spw figure 6. keyscan timing kbint scan enable active active key depressed key command key command key depressed figure 7-1. single keypress/single read kbint scan enable active key depressed null command key command figure 7-2. single keypress/multiple read
? semiconductor MSC7170-01 13/27 fedl7170-03 k bint scan key 1 depressed e nable key command key command key 2 depressed active figure 7-3. multiple keypress/multiple interrupt figure 7. typical cases of keyscan operation
? semiconductor MSC7170-01 14/27 fedl7170-03 functional description the MSC7170-01 (dot matrix vf segment driver) in conjunction with the msc7171 (dot matrix vf grid driver) is capable of controlling a variety of dot matrix vf displays and keyboards. the MSC7170-01 is designed to drive the anodes of up to 32 dot matrix digits in two lines. each digit is a 5 7 matrix of anodes, or dots, which requires a total of 70 segment driver outputs. there are two extra segment outputs for supplying drive to dedicated annunciators. the grid drivers of the msc7171 are controlled by the MSC7170-01 through a two-line serial interface and a duty cycle control line, duty (see application circuit). additionally, the MSC7170-01 provides 10- bit digital dimming of all display data, a 5 6 keyscan function allowing control of up to 30 key pads and a low-power standby mode. the MSC7170-01 is controlled through a standard spi interface. all MSC7170-01 internal timings are generated through an external 4 mhz (typ) ceramic oscillator. one display cycle is defined as up to 16384 periods of the 4 mhz (250 ns) reference in increments of 1024 periods, one for each pair of digits displayed. display intensity is determined by the duty cycle of the duty output within one display increment divided by the total number of increments, or character pairs, displayed (see display duty cycle set and number of display digit pairs set commands below). the maximum duty cycle is defined as 976 out of 1024 increments or 95.3 percent. the MSC7170-01 is capable of synchronizing the duty signal with an ac filament to avoid visible flicker during dimming conditions. this is required in vf tubes of greater than 100 mm, equivalent to 14 digits, in length. synchronization is accomplished by alternately initiating display cycles coincident with rising and falling edges of the filament voltage. upon completion of a rising/falling edge display cycle, the MSC7170-01 will wait for a falling/rising edge before initiating the next display cycle. the MSC7170-01 detects rising and falling edges of a cmos- compatible sync input derived directly from the filament voltage. the amount of hold time between display cycles varies between no delay as a minimum and the period of the filament voltage as maximum. the amount of delay should be consistent for all display cycles assuming that the filament frequency is well defined. the MSC7170-01 is controlled through a serial peripheral interface (spi) compatible communi- cations port. the spi is a high-speed synchronous serial i/o port that shifts a serial bit stream of eight data bits into or out of a device at a bit transfer rate programmed in a controlling device. the figure below shows a typical connection of the spi for communications between a master (radio microprocessor) and slave (MSC7170-01). three i/o pins are associated with the spi interface spi slave-in master-out (simo), spi slave-out master-in (somi), and spi serial clock (sclk). additionally, a separate input pin is used to enable the MSC7170-01 to communicate with the microprocessor through this interface.
? semiconductor MSC7170-01 15/27 fedl7170-03 serial input buffer master simo somi sclk microprocessor msb lsb shift register serial input buffer slave simo somi sclk MSC7170-01 msb lsb slave in/master out slave out/master in enable serial clock shift register spi master/slave connection the microprocessor provides the serial clock (500 khz typ.) to all devices on the spi network with a clock polarity of 1 (inactive level is high). data is transferred from the master (microprocessor) to the salve (MSC7170-01) over the simo line, while data is transferred from the slave to the master over the somi line. data is clocked out of the transmitting device on the falling edge of sclk and latched into the receiving device with the rising edge of sclk. all data transmissions are made msb (b7) first. a typical data transfer cycle between the microprocessor and the MSC7170-01 is initiated by first bringing the enable line low. the first byte transmitted defines the command or operation to be executed. all remaining bytes received, prior to enable being returned high, are treated as data bytes for that operation. each command or operation executed requires a separate enable transfer cycle. the maximum waiting period between byte transfers, measured from msb to lsb, is 20 msec. all activity on the sclk and simo pins while enable is high is ignored. additionally, the somi pin shall be in a tri-state condition when enable is high so that other spi devices on the network may drive the line without contention. the MSC7170-01 controls up to 30 key pads via a 5 controls up to 30 key pads via a 5 6 key scan circuit. col1 to 6 (inputs) and row1 to 5 (outputs) are connected to an external switch matrix with an impedance of 500 w max. the row1 to 5 outputs start scanning only when a depression or release of any key is detected. upon completion of the first keyscan cycle, see figure 6, the keyboard interrupt, kbint , output is pulled low to indicate availability of new keyscan data. the keyscan circuit continues to scan and kbint remains low until the keyscan data has been read using the keyscan data output command. in the event of a multiple key depression, a second interrupt will be generated following the clearing of the first interrupt. a stuck key switch will not generate multiple interrupts since only state transitions are detected by the keyscan circuitry. keyscan data may be read without stopping the keyscan by using the null command. the keyscan data is transmitted to the microprocessor by rows as shown in the output data bytes section. the output of keyscan data wraps around to the first byte for spi transactions of more than six bytes. after completion of the last keyscan cycle all row outputs go to low level.
? semiconductor MSC7170-01 16/27 fedl7170-03 key switch data is latched internally for transfer to the microprocessor via the spi port. the microprocessor may use kbint as an interrupt request or for polling the MSC7170-01 to determine when new keyscan information is available. as an alternative for polling, the MSC7170-01 continuously outputs a status byte during any spi transaction, with the exceptions of the null command and the keyscan data output command. an all zeros (00h) byte indicates the presence of new keyscan information while all ones (ffh) indicate no new keyscan information. for the null and keyscan data output commands, the first byte output is still the status byte followed by five bytes containing the data from the five keyscan rows as described above and in the output data bytes section. the status byte is reset upon completion of a keyscan data output command in the same fashion as kbint . the MSC7170-01 can also be commanded into a low power or "standby" mode (see mode set command). in this mode all operation, including the internal oscillator, of the MSC7170-01 ceases. the only exception is the key scan detection circuitry which, on any key pad activity (depress or release), will cause the MSC7170-01 to return to normal operation. the msc7170- 01 will be fully operational within 10 msec (max) after return to normal operation. the wake-up cycle includes a full scan of the key matrix. kbint will be pulled low to indicate full wake-up. normal operation is also resumed when the enable line is taken low. in this case, a scan of the key matrix is not executed, nor is the kbint line pulled low to indicate full wake-up. the reset and enable lines shall be maintained at logic high levels during standby operation. all segment outputs go to a high impedance state while in standby mode. the spi interface lines (slck, simo, and somi) will not interfere with the operation of the spi network when the standby mode is properly selected. to ensure correct operation of the spi network, the standby mode of the MSC7170-01 should always be selected before the logic supply is switched off. the following sequence of events should be followed to enter standby mode: 1) set duty cycle to zero percent 2) turn off high voltage (v disp ) 3) send low power (standby) "on" command following wake-up, the high voltage should be turned on prior to setting a duty cycle greater than zero percent. the MSC7170-01 may be commanded into blank and lamp test modes. for blank mode, the duty and segn-1 to segn-35 outputs remain at a continuous low level while the segn36 outputs assume a high level. the outputs remain at this level until the command is deselected. for lamp test mode, the duty output assumes a maximum duty cycle condition and the segn outputs are all forced to the on condition regardless of input data. the MSC7170-01 accepts a reset signal from the microprocessor or other controller. there shall be no internal pull-up resistor on this signal. the state of the MSC7170-01 following a reset is as follows: a) all segment driver outputs are low b) the number of display digits is 16 2. c) the display duty cycle is set to 0 d) display data buffers are not cleared e) spi registers are reset f) keyscan registers are reset
? semiconductor MSC7170-01 17/27 fedl7170-03 the MSC7170-01 is protected against thermal overload or other failure caused by extreme display configurations (e.g. lamp test) or due to output short circuits to high voltage supply, ground, or another output. these shall be no performance degradation once the short circuit is removed.
? semiconductor MSC7170-01 18/27 fedl7170-03 commands description address setup command this command is used to setup a start position of display character code writing and must be executed before the desired character code is sent. in applications using less than the full 16-digit pair capability, only the first 2n memory locations are used. for example, if n = 12-digit pair is selected, only addresses 0 through 23 are used. row 1 display data (seg1 outputs) is stored in addresses 0 through 11 while row 2 display data (seg2 outputs) is stored in addresses 12 through 23. all bytes following bytes 1 and 2 are treated as character code data bytes. address 0 is set after reset. a4 to a0 : 00000=00h=0 : 11111=1fh=31 d7 d6 d5 d4 d3 d2 d1 d0 byte 2 x x x a4 a3 a2 a1 a0 c7 c6 c5 c4 c3 c2 c1 c0 byte 1 1000 xxxx no. instruction byte c7 c6 c5 c4 c3 c2 c1 c0 0 address setup 11000 xxxx 2 x x x a4 a3 a2 a1 a0 1 character code setup 11001 xxxx 2 b7b6b5b4b3b2b1b0 2 display duty cycle setup 11010xxdc9dc8 2 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 3 display digits setup 11011n3n2n1n0 4 mode setup 11100xm2m1m0 5 cursor setup 11101 xxxx 2 c1-7 c1-6 c1-5 c1-4 c1-3 c1-2 c1-1 c1-0 3 c1-15 c1-14 c1-13 c1-12 c1-11 c1-10 c1-9 c1-8 4 c2-7 c2-6 c2-5 c2-4 c2-3 c2-2 c2-1 c2-0 5 c2-15 c2-14 c2-13 c2-12 c2-11 c2-10 c2-9 c2-8 6 keyscan data output 11110 xxxx 7 null 100000000
? semiconductor MSC7170-01 19/27 fedl7170-03 character code setup command this command is used to specify the character to be displayed in the display location previously specified by the address setup command. a built-in automatic address increment function simplifies writing more than one display character code. all bytes transmitted after byte 2 are treated as character code data for successive locations. the internal address counter will be automatically incremented from the address set using the address set command through address 31 (or character 32), while executing valid write cycles, regardless of the number of digit pairs as defined using the number of display digits setup command. in the event that additional data is input to the MSC7170-01 following a valid write to address 31, the address counter will wrap-around and continue to increment (to address 0 etc.) with write cycles disabled. this prevents overwriting of the memory. b4 to b0 : 8-bit character code select one of 256 codes d7 d6 d5 d4 d3 d2 d1 d0 byte 2 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 byte 1 1001 xxxx display duty cycle setup command this command is used to set the duty cycle of the display. the time allocated to a 1-digit display is 1024t, where t is the period of the internal oscillator (f osc ). the display time for each digit may be specified as 0 to 976t in increment of t. entries greater than 976 default to 976. the display duty cycle is calculated by dividing the input duty cycle value, dc, by 1024 times the number of digits, n, commanded to display. note that the percent duty cycle depends on how many digits (characters) are displayed. d7 d6 d5 d4 d3 d2 d1 d0 byte 2 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 c7 c6 c5 c4 c3 c2 c1 c0 byte 1 1010xxdc9dc8
? semiconductor MSC7170-01 20/27 fedl7170-03 number of display digits setup command this command is used to set the number of digits to be displayed. the number of digits selectable ranges from 1 to 16. n3 to n0 : 0000=0h=16-digit pair c7 c6 c5 c4 c3 c2 c1 c0 byte 1 1011n3n2n1n0 : 0001=1h=1-digit pair : : 1111=fh=15-digit pair c7 c6 c5 c4 c3 c2 c1 c0 byte 1 1100xm2m1m0 m2 m1 m0 mode 0 0 0 normal operation 0 0 1 lamp test (all display on) 0 1 0 low power 0 1 1 normal operation 1 0 0 blank (all display off) 1 0 1 normal operation 1 1 0 normal operation 1 1 1 normal operation mode setup command this command is used to select an operation mode for the MSC7170-01. lamp test and blank modes turns all 36 segments of each displayable digit (as set by the number of display digits setup command) to the on and off states respectively. the contents of the display buffer are not affected by either of these modes. the normal operation mode returns after reset. low power mode is described earlier.
? semiconductor MSC7170-01 21/27 fedl7170-03 cursor setup command this command is used to specify the on/off state of cursor segments (segn-36) in the display. the cursor outputs are issued inversely to allow an external pnp transistor to be used in applications requiring high current drive capability. therefore, a logic high, l, in a given bit position will turn on the associated cursor. in applications requiring low current (less than 15 ma) drive capability, the cursor outputs may drive the vf display tube directly. in these applications, setting to "0" turns on the cursor. d7 d6 d5 d4 d3 d2 d1 d0 byte 2 byte 3 byte 4 byte 5 c7 c6 c5 c4 c3 c2 c1 c0 byte 1 1101 xxxx c1-7 c1-6 c1-5 c1-4 c1-3 c1-2 c1-1 c1-0 c1-15 c1-14 c1-13 c1-12 c1-11 c1-10 c1-9 c1-8 c2-7 c2-6 c2-5 c2-4 c2-3 c2-2 c2-1 c2-0 c2-15 c2-14 c2-13 c2-12 c2-11 c2-10 c2-9 c2-8 keyscan data output command this command is used to read keyscan data via the spi interface and has no effect on the operation or state of the display portion of the MSC7170-01. upon completion of this command the kbint output is reset to its non-active state and the keyscan function is stopped. all bytes after byte 1 are ignored. c7 c6 c5 c4 c3 c2 c1 c0 byte 1 1110 xxxx null command this command has the same function as the keyscan data output command with the exception that kbint is not reset and the keyscan function continues to scan the key matrix. the keyscan may stop momentarily to prevent changing data while data output is in progress. all bytes after byte 1 are ignored. c7 c6 c5 c4 c3 c2 c1 c0 byte 1 00000000
? semiconductor MSC7170-01 22/27 fedl7170-03 output data byte description ? status output the following byte is output from the MSC7170-01 during execution of every spi command with the exceptions of the keyscan data output and null commands. the status byte is issued for each byte of the input command sequence. ? keyscan data output the following bytes are output from the MSC7170-01 during execution of the keyscan data output and null commands. the output of keyscan data wraps around to byte 1 for transactions of more than six bytes. d7 d6 d5 d4 d3 d2 d1 d0 byte 1 x x s16 s15 s14 s13 s12 s11 byte 2 x x s26 s25 s24 s23 s22 s21 byte 3 x x s36 s35 s34 s33 s32 s31 byte 4 x x s46 s45 s44 s43 s42 s41 byte 5 x x s56 s55 s54 s53 s52 s51 row 1 row 2 row 3 row 4 row 5 sij : i=row1 to 5, j =col1 to 6 sij=1: switch on sij=0: switch off d7 d6 d5 d4 d3 d2 d1 d0 byte 1 s7 s6 s5 s4 s3 s2 s1 s0 s7 to s0: indicates change status from last spi transaction 00h = change, ffh = no change status
? semiconductor MSC7170-01 23/27 fedl7170-03 character codes and character patterns f e d c b a 9 8 7 6 5 4 3 2 1 0 f e d c b a 9 8 7 6 5 4 3 2 1 0 msb: d7 - d4 lsb: d3 - d0 note: these character patterns are user programmable and can be selected by mask option.
? semiconductor MSC7170-01 24/27 fedl7170-03 correspondence between segment outputs and vf display tube dots vf dot: ic pin: vf dot: ic pin: vf dot: ic pin: vf dot: ic pin: vf dot: ic pin: vf dot: ic pin: vf dot: ic pin: 1-1 segn-1 1-2 segn-6 1-3 segn-11 1-4 segn-16 1-5 segn-21 1-6 segn-26 1-7 segn-31 2-1 segn-2 2-2 segn-7 2-3 segn-12 2-4 segn-17 2-5 segn-22 2-6 segn-27 2-7 segn-32 3-1 segn-3 3-2 segn-8 3-3 segn-13 3-4 segn-18 3-5 segn-23 3-6 segn-28 3-7 segn-33 4-1 segn-4 4-2 segn-9 4-3 segn-14 4-4 segn-19 4-5 segn-24 4-6 segn-29 4-7 segn-34 5-1 segn-5 5-2 segn-10 5-3 segn-15 5-4 segn-20 5-5 segn-25 5-6 segn-30 5-7 segn-35
? semiconductor MSC7170-01 25/27 fedl7170-03 application circuit v ss2 MSC7170-01 1 2 3 4 5 6 5 4 3 row col 2 1 s21 s22 s23 s24 s25 s26 s31 s32 s33 s34 s35 s36 s41 s42 s43 s44 s45 s46 s51 s52 s53 s54 s55 s56 s11 s12 s13 s14 s15 s16 keyboard matrix v dd simo somi sclk enable from microprocessor 5v reset kbint oscl osco s standby data clock duty standby data clock duty v ss1 p msc7171 v ss p v dd s v disp grid1-12 12 seg1-1 to seg1-35 35 seg2-1 to seg2-35 35 v disp sync nc seg1-36 seg2-36 p display voltage and ac filament supply v disp v grid fil1 fil2 p 12 filament dot matrix vf display tube resonator
? semiconductor MSC7170-01 26/27 fedl7170-03 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp100-p-1420-0.65-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.29 typ. mirror finish
? semiconductor MSC7170-01 27/27 fedl7170-03 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 2000 oki electric industry co., ltd. printed in japan

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